In PWM inverters and converters, the phase voltage is composed of a series of square pulses of short duration compared to the fundamental frequency. These pulses are of constant magnitude and variable pulse widths.
The output voltage waveform of an inverter is a pulse train whose polarity reverses periodically to provide the fundamental frequency. The repetition rate of the output pulse train is the carrier frequency f.sub.c, if a triangle comparison PWM method is used. Variation of the width of the pulses that make up each half period controls the RMS voltage magnitude. This variation or modulation is achieved in practice by many techniques. A common technique is known as the triangulation or subharmonic method in which the duration of pulses that control switches in power circuit is determined by the crossover points of two reference signals: a high-frequency triangular voltage wave and a sinusoidal voltage varying at fundamental frequency. The PWM signal is used to control the switches in a bridge at f.sub.c.
Ideally, the transistors in each leg of the bridge circuit instantaneously turn off when the PWM signal changes to its inactive state, for example, changes from logic 1 to logic 0. However, in practical circuits utilizing transistor-type circuits, instantaneous turnoff of the transistors is not realizable. For example, when a PWM signal supplied to a pair of switches in a bridge leg changes from logic 1 to logic 0, the first transistor does not turn fully off before the second turns on. This is because a finite amount of time is required for a transistor to come out of saturation after the PWM drive signal changes to its inactive state (logic 0). This results in simultaneous conduction of the two transistors in the bridge leg. Since the two transistors form a series connection across the power supply, their simultaneous conduction results in excessive current and the destruction of the transistors. To avoid this problem, an intentional blanking interval is introduced into the PWM signal driving the bridge circuit. In other words, the turn-on of the second switch in the inverter leg is delayed by a blanking time t.sub..DELTA., to avoid a short circuit through the inverter leg. The duration of the time delay t.sub..DELTA. is sufficient to ensure that both transistors in the inverter leg are off before allowing a transistor in the pair in the bridge circuit to turn on. The blanking interval time is also known as the dead time.
Since both the switches are off during the blanking time, the line-to-neutral voltage during that time interval depends on the direction of the load current. When a load current i.sub.A is positive (going from inverter to load), this results in a voltage loss .DELTA.U.sub.A =U.sub.DC *[t.DELTA./T.sub.C ] and when the current is negative, in a voltage gain .DELTA.U.sub.A =U.sub.DC *[-t.DELTA./T.sub.C ], where t.sub..DELTA. is equal to the blanking time interval, T.sub.C is equal to the period of the carrier frequency and U.sub.DC is the DC buss voltage. It is desirable to minimize .DELTA.U.sub.A.
Assuming a three-phase, three-legged power conversion bridge (converter or inverter), the same analysis applies to the second leg B and third leg C. The distortion in U.sub.A, U.sub.B, and U.sub.C at zero crossings of phase currents in i.sub.A, i.sub.B, and i.sub.C results in harmonics, such as third, fifth, seventh, and so on of the fundamental frequency in the inverter or converter output.
The need for compensation of a blanking time interval is well known (see U.S. Pat. No. 4,562,386 by Goff et al, filed Jan. 26, 1984, issued Dec. 31, 1985 and entitled "Current Sense Demodulator"), as are the problems with harmonics caused by the blanking interval which have also long been recognized (Ned Mohan, Tore M. Underland, William P. Robbins, "Power Electronics Converters, Applications, and Design", John Wiley & Sons, New York, 1989, pp 141-144).
One method of compensating for blanking interval loss is disclosed in U.S. Pat. No. 4,547,719, filed Jan. 25, 1983 and issued Oct. 15, 1985 to Sakamoto et al. which relies upon voltage feedback. This arrangement employs a voltage converting circuit for generating an impressed voltage from an armature voltage U.sub.C, a subtracting circuit for calculating the difference between the output voltage of a holding circuit and the output voltage of the voltage converting circuit, and an integrating circuit for integrating the difference generated by the subtracting circuit. In other words, the output voltage of the inverter circuit is fed back to a pre-stage of the PWM circuit to raise the gain using the feedback loop. However, with an arrangement in which a microprocessor is used as a portion of the motor control circuit, it is necessary to provide separate analog circuits for these feedback loops. This process must be implemented by fast analog circuits and cannot be performed quickly enough by the microprocessor. The solution is complicated in construction and carried out at high cost.
A second apparatus for compensating for PWM blanking time is disclosed in U.S Pat. No. 4,719,400 filed Oct. 19, 1983 and issued on Jan. 12, 1988 to Kurakake et al. Kurakake discloses a motor control apparatus including an arithmetic circuit for calculating the current command, a holding circuit for holding the current command, a PWM circuit for pulse-width-modulating an output signal from the holding circuit and provided with a dead zone with respect to the output signal, and a transistorized amplifier circuit for controlling a motor by a PWM signal. The arithmetic circuit adds a compensating signal to the current command to compensate for motor control losses due to the blanking time and delivers the result to the holding circuit. This discloses a solution to the problem of losses and distortion that result from the blanking time, but creates another problem in that the compensation is performed all the time. For example, when the PWM circuit is commanded to be near saturation (full conduction of the complementary switches in a power circuit), an additional compensating signal may bring the PWM circuit into saturation and provide excessive load voltage. On the other hand, when the PWM circuit is commanded to go into saturation by the reference voltage, a blanking interval voltage deviation signal can bring it out of saturation, thereby unintentionally reducing the load voltage. In sum, compensation performed all the time causes additional load current distortion when the PWM circuit operates near saturation.